The present invention relates to a clocked logic circuit including a CMOS synchronous gate and, more particularly, to an improvement of a CMOS clocked logic circuit in which a clock race problem caused by an overlap of two clock phases is avoided.
In a conventional synchronous CMOS logic circuit, signals to be gated are supplied to asynchronous gate circuits in synchronism with clock signals during the signal transfer, thereby obtaining a desired logic operation. However, when an asynchronous CMOS gate circuit is used together with synchronous CMOS gate circuits in a manner that the asynchronous circuit is inserted between or provided among the synchronous circuits, a clock race problem due to the overlap of two clock phases (clock skew) occurs, resulting in erroneous operation. Such a clock race problem is chiefly caused by the slow switching speed of CMOS gates.
The "clock race problem" is a known subject to a skilled person in the art. As for the details of "clock race problem", reference should be made to the following literature:
N. F. Goncalves, et al., "A Racefree Dynamic CMOS Technique for Pipelined Logic Structures" in ESSCIRC Dig. Tech. Papers, 1982, pp. 141-144.